Zenex Partners

Senior DFT Engineer

Hardware Engineer in Austin, TX

Posted 2020-02-14

Currently looking for an experienced Senior DFT Engineer to fill an opening with a company located in Austin, Texas. Interested candidates should have 2+ years of experience with Synopsys ATPG TetraMAX or Mentor Fast scan.

Responsibilities for Senior DFT Engineer:
• Use industry standard tools to implement scan in complex IP, generate high coverage ATPG patterns utilizing scan compression and verification.
• Analyze scan coverage, implementation issues and come up with strategies to address quality and efficiency.
• Build verification environment to run and debug gate level simulations.
• Document scan designs and maintain guidelines for best scan design practices.
• Define, develop, and improve scan design process flows and methodologies for continuous improvement.
• Run, debug, and perform diagnostics on scan patterns post-silicon on a production and/or debug tester

Requirements for Senior DFT Engineer:
• Strong problem solving skills.
• Have 2+ years of experience with Synopsys ATPG TetraMAX or Mentor Fastscan.
• Knowledge of low-power design methodologies.
• Must have scripting and automation skills – Preferred Python and Perl, TCL.
• Experience with synthesis, static timing analysis, and ATPG modeling.
• Knowledge of stuck-at, transition, IDDQ, and other advanced fault models.
• Self-motivated, able to work independently, excellent communication skills,
excellent presentation skills for design reviews, and ability to excel in cross
functional team environment.
• MSEE or BSEE with 5+ years relevant experience preferred (or equivalent
education and experience)

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