Contribute to a leading-class multi-use platform including development, design, and deployment of new capabilities for GPS/GNSS applications.
Develop hardware in Verilog RTL to support and enhance capabilities for software-defined radios
Develop requirements and architect new features.
Develop C, C++, and Python to support and enhance capabilities for software-defined radios.
Develop hardware simulations and software regression tests to verify correct operation of firmware and software.
Support integration, test, verification, and bug resolution for the release of new firmware and software builds.
Perform analysis on collected data to ensure correct performance.
Create and maintain documentation and procedures to support sustainable team development activities.
Occasional collection of data at remote locations and occasional outdoor deployments.
Other related functions as assigned.
Bachelor's degree in physics, engineering, computer and information science or other related applied sciences. Three years of demonstrated ability in applied research. Demonstrated track record delivering digital designs in Verilog RTL development targeting FPGAs
Applicant must have a dynamic skill set, willing to work with new technologies, be highly organized and capable of planning and coordinating multiple tasks and managing their time. The position will require attention to detail, effective problem-solving skills and excellent judgment.
Ability to work independently with sensitive and confidential information, maintain a professional demeanor, work as a team member without daily supervision and effectively communicate with diverse groups of clients. Able to work under pressure and accept supervision.
Regular and punctual attendance. US Citizen. Applicant selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information at the level appropriate to the project requirements of the position.
Master's degree in Electrical Engineering, Computer Science or Physics and five or more years of experience. Experience with Verilog RTL development targeting Xilinx FPGAs using the Vivado design environment. Experience implementing DSP algorithms in hardware. Experience in C++, Python, and data analysis. Cumulative GPA of 3.0.
Applied Research Laboratories, the University of Texas at Austin (ARL:UT), is a Department of Defense University-Affiliated Research Center (UARC). Since 1945, ARL:UT has been engaged in sponsored research dedicated to improving our national security through applications of acoustics, electromagnetics, and information sciences. As the largest and one of the oldest research units of the university and a member of the Vice President for Research portfolio, ARL:UT is highly engaged in the three traditional roles of a major university - research, education, and public service.
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ARL:UT is home to some of the world’s most advanced research teams in the areas of acoustics, electromagnetics, and information sciences. Our sponsors include branches of the U.S. Department of Defense, NASA, NIH, and agencies from the Intelligence Community.
Research and development professionals make up the majority of ARL:UT's total staff of approximately 750, and opportunities exist for all degree-level candidates in aerospace, computer, electrical, and mechanical engineering, as well as in computer science, physics, and mathematics.
ARL:UT offers relocation packages, exceptional benefits, staff education programs, and a casual work environment. Employees enjoy the added benefit of living in the dynamic city of Austin.The culture here supports a high quality of life and fosters creativity and innovation. Our facility is located at the J.J. Pickle Research Campus and located directly across the street from an area known as the Domain; a great outdoor shopping and restaurant area. The campus offers it's own onsite amenities such as dining option(s), workout area and other perks. Each year during the December holiday season the laboratory closes (with the exception a skeleton crew) for a typical 1 week minimum with paid holiday time off. ARL:UT will be expanding into a new multi-story building during the next few years and experiencing a time of great growth and opportunity for job seekers.
Java, C, C++, Python, Linux
Candidates are considered to have officially applied for the position once they complete the job application instructions/process (per the job posting). Candidates will typically be screened 1-2 times via phone and then interviewed onsite.
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